1. Field of the Invention
The present invention relates to a routing method for routing a plurality of signal traces out of corresponding bumper pads in a multi-layer circuit board, and more particularly, to a tile-based routing method for routing a plurality of signal traces and a plurality of shielding traces in the multi-layer circuit board.
2. Description of the Prior Art
In modern society with developed computer technology, the computer system, which comprises a plurality of integrated circuits, has been utilized in a broad spectrum of fields. For example, household appliances with automatic control systems, mobile communication devices, and personal computers utilize integrated circuits to perform certain functions. The main body of the IC is a die manufactured by a prior-art semiconductor process. The manufacturing process of the die starts from forming a wafer. Each wafer is divided into a plurality of regions. On each region, many circuits are formed through the prior art semiconductor process. In the end, each processed region on the wafer is sliced to generate a plurality of dies. After the required die is obtained, it requires a specific way to electrically connect the processed die with a circuit board such as a printed circuit board (PCB). Therefore, the die is capable of acquiring its operating voltage from the PCB for performing a predetermined operation. For instance, suppose that the IC die corresponds to an encoder circuit. After the encoder circuit is provided with an appropriate operating voltage, the IC die (encoder circuit) is capable of encoding data inputted from the circuit board, and then returns the encoded data to the circuit board.
Certain IC dies, called wire-bond IC dies, are fabricated with metal bonding pads only along their periphery. These peripheral pads serve as terminals for connecting the die to external signals, including control signals, power and ground. Typically, the wire-bond IC die is mounted within a plastic or ceramic package having multiple pins, and wire connections are made between the die's bonding pads and the package's pins. However, the above-mentioned packaging method has its limitations. First, because only the periphery of the die is used for external connection pads, the number of such pads for a given sized die is limited. In particular, advances in technology which permit more and more gates to be placed within a given die area have resulted in an increased demand for such pads, particularly power and ground pads. In certain cases, the design requires more pads than can be provided solely at the die's periphery. Second, when all the pads are provided only at the die's periphery, additional routing is required to bring the corresponding signals, particularly power and ground signals, to the interior logic of the die. Third, in wire-bond dies, the wire connections between the die and the package pins introduce additional resistance and inductance, which sometimes may spoil the die's performance.
The flip-chip packaging, which is developed to overcome the above-mentioned problems, has become a more preferable packaging method nowadays. The flip-chip packaging technology allows the overall package size to be made significantly compact. The connections between the IC die and the exterior electrical components offer a lower inductance and resistance electrical connection than wire-bond packaging. In addition, the shorter connection path of power and ground improves the power supplement quality. However, even based on the flip-chip packaging technique, a basic and inevitable principle is that the die size should be subject to the size and quantity of the spreading bumpers. Due to that nowadays, companies developing and manufacturing electronic products are challenged by a blooming market demand for smaller, more efficient, and a higher performance product, bringing down the relative die size to meet the cost concern becomes a crucial issue.
For achieving the space-saving advantage, a multi-layer substrate (circuit board) should also be included in an electrical system. The current fabrication process of the multi-layer substrate could be sorted into different methods, including a laminated substrate, and a build-up substrate. The build-up substrate among them would be the most suitable one for a high pin-count application to extend the density capability of the conventional circuit board due to its thin signal trace (30 μm). Please refer to both FIG. 1 and FIG. 2. FIG. 1 is a schematic diagram showing a typical arrangement of a die 10 located on a 6-layer build-up substrate 12, and FIG. 2 is a schematic diagram of an embodiment of the 6-layer build-up substrate 12 shown in FIG. 1. The 6-layer build-up substrate 12 includes 4 build-up layers (layers 12A, 12B, 12E, and 12F) for routing a plurality of signal traces. Each build-up layer provides a 25/25 μm trace width/space, and an 110 μm via 12G. The other two traditional layers C, D respectively provides a 100/100 μm trace width/space and a 440 μm via 12H. Due to the structure of the 6-layer build-up substrate 12, when the 6-layer build-up substrate 12 is actually implemented, only the 4 build-up layers (layers 12A, 12B, 12E, and 12F) would be used for signal-trace routing functions. The remaining layers (two traditional layers 12C, 12D) can be used to provide power and ground spreading due to that the wide via (440 μm) 12H between the layer 12C and the layer 12D is unfavorable for many signal traces to pass through. Please refer to FIG. 3, which is a detailed schematic diagram describing the region 14 shown in FIG. 1. The embodiment in FIG. 3 shows a plurality of signal traces 18 spread from the die 10 and routed in the 6-layer build-up substrate 12 shown in FIG. 2. The embodiment in FIG. 3 shows that all the signal traces 18 are designed to be routed in the build-up layers 12A, 12B. Therefore, all the signal traces 18 can be classified into first-layer traces 18(1) and second-layer traces 18(2), respectively representing the signal traces 18 routed in the build-up layers 12A and in the build-up layers 12B. Please also refer to FIG. 4, which is a schematic diagram illustrating a plurality of bumper pads 20 arranged over the die 10 as shown in FIG. 1 and FIG. 3. The plurality of bumper pads 20 will be used as the input/output terminals for the die 10. The signal traces 18 as shown in FIG. 1 or FIG. 3 can be routed out of a plurality of corresponding bumper pads 20 located on either a periphery area of the die 10, called die periphery 22, or a center area 24 of the die 10.
Please return to refer to FIG. 1 and FIG. 2. When those signal traces 18 start to fan out from the bumper pads 20 of the die 10, the assumed area 16 is not so wide to accommodate so huge wide vias 12H. Therefore, there would be very few signal traces 18 being routed down to the build-up layers 12E, 12F. That also explains why the signal traces 18 are almost routed in the build-up layers 12A, 12B (top 2 layers) as shown in FIG. 3. As you can see in the FIG. 4, when using flip-chip techniques, a typical IC die 10 often will contain hundreds of bumper pads 20. Routing the signal traces 18 from each of these bumper pads 20 to the appropriate position on the die 10 can therefore become a complicated task. In addition, these large amounts of bumper pads 20 have to be assigned closer to get a more effective use of the routing space on the substrate 12. In the meanwhile, the (6-layer) build-up substrate 12 is required to provide a more aggressive signal routing density within a certain area and higher flexibility of fanning out the signal traces 18. However, the higher signal trace density and lower die size will also introduce the smaller space among all the signal traces 18, which would worsen the cross-talk effect (mostly the capacitive cross-talk) between signals and bring down the signal quality.